Unlike conventional random access memory (RAM) chip technologies, in magnetic RAM (MRAM) data is not stored as electric charge, but by magnetic polarization of storage elements. The elements are formed from two magnetically polarized plates, each of which can maintain a magnetic polarization field, separated by a thin insulating layer, which together form a magnetic tunnel junction (MTJ). One of the two plates is a permanent magnet (hereinafter “fixed layer”) set to a particular polarity; the polarization of the other plate (hereinafter “free layer”) will change to match that of a sufficiently strong external field. A memory device may be built from a grid of such “cells”.
Reading the polarization state of an MRAM cell is accomplished by measuring the electrical resistance of the cell's MTJ. A particular cell is (conventionally) selected by powering an associated transistor which switches current from a supply line through the MTJ to a ground. Due to the tunneling magnetoresistance effect, the electrical resistance of the cell changes due to the relative orientation of the polarizations in the two magnetic layers of the MTJ. By measuring the resulting current, the resistance inside any particular cell can be determined, and from this the polarity of the free writable layer determined. If the two layers have the same polarization, this is considered to mean State “0”, and the resistance is “low,” while if the two layers are of opposite polarization the resistance will be higher and this means State “1”.
Data is written to the cells using a variety of schemes. In conventional MRAM, an external magnetic field is provided by current in a wire in proximity to the cell, which is strong enough to align the free layer.
Spin-transfer-torque (STT) MRAM uses spin-aligned (“polarized”) electrons to directly torque the domains of the free layer. The current to write to the cells through this mechanism is less than the write current for conventional MRAM. Furthermore, no external magnetic field is required, so that adjacent cells are substantially unaffected by stray fields. This write current further decreases as the memory cell size scales down, which is a critical benefit as the semiconductor technology continues to scale to higher device pitch density.
One significant determinant of a memory system's cost is the density of the components on the chip. Smaller components, and fewer components per “cell,” mean that more “cells” may be packed onto a single chip, which in turn means more chips can be produced at once from a single semiconductor wafer and fabricated at lower cost and improved yield.
In addition, the manufacturing process flow affects cost, with more mask processes contributing to increased overall manufacturing costs. When fabrication of conventional MRAM requires a number of mask processes dedicated solely to the fabrication of the magnetic tunnel junction (MTJ) structure, costs are further increased. Because processing cost is a serious consideration in implementing integration of features in an integrated circuit device, any improvement in the design and process flow that eliminates masks and associated processes is advantageous. A difference in one mask process can save significant costs. Accordingly, there is a need for improved methods for integrating MRAM fabrication in the semiconductor manufacturing process flow. Moreover, any design that relaxes alignment of critical dimension features would be desirable.